1. Field Of the Invention
The present invention relates to an apparatus and method for testing a plurality of memory cells contained in a memory device. More particularly, the present invention relates to testing circuit and method for reading and writing in parallel a greater number of data bits during a single clock cycle than is capable of being read from or written into the plurality of memory cells through its predetermined number of external input/output data pins or pads (hereinafter referred to as "I/O data pins").
2. Description of Related Art
In today's semiconductor industry, memory devices such as static random access memory (SRAMs), random access memory (RAMs), direct random access memory (DRAMs) and the like are well known in the art. Such semiconductor memory devices are capable of being fabricated in a number of different configurations depending on its desired memory size and its desired number of I/O data pins. For example, a memory device containing approximately one million bits, or more specifically one million memory cells, could be fabricated as a 1M.times.1 memory device having only one I/O data pin. Similarly, the above-indicated memory device could be designed as a 256K.times.4 device having four I/O data pins, an 128K.times.8 device having eight I/O data pins, and so on. Accordingly, the presence of additional I/O data pins allows a greater number of bits to be read or written during the same clock cycle. In general, memory devices are commonly referred to by the number of I/O data pins therein. For instance, a n.times.8 memory device (where n is equal to a whole number) is commonly referred to as a " .times.8 device", indicating that it has eight I/O data pins to enable the device to read or write eight bits of data in parallel into eight memory cells for each clock cycle.
Before placing a semiconductor memory device into the marketplace, its manufacturer tests each memory cell contained therein to determine whether it is functioning properly (i.e., whether it is properly retaining stored data). It is commonly known that conventional memory testing techniques are governed by the number of I/O data pins in the memory device. As shown in FIG. 1, a .times.1 memory device 1 has only one I/O data pin 2 so that only one memory cell can be tested during each read or write cycle.
Semiconductor memory testing is usually accomplished by inputting bits of data into at least one internal write buffer 4 from a buffering device, called a data-in buffer 3, which regulates the inputted data bits. The data bits comprise one of two opposite polarities (either a "1" or "0"). The write buffer 4, in turn, drives at least one write bus 5 to write a first selected polarity into every memory cell 6 contained in the device. Thereafter, a first memory cell is read to confirm that a polarity stored in the memory cell is equivalent to the first selected polarity. This is done in a manner similar to the write operation to read the stored polarity from a memory cell 6, where at least one read bus 7 is activated causing at least one output buffer 8 to drive the stored polarity into the I/O data pin 2 or any other designated I/O data pin.
If these polarities are the same, then a second of the two polarities is inputted into the first memory cell and read therefrom. If such polarities are also equivalent, then the first memory cell is determined to be functioning properly. This testing procedure is continued until every cell in the semiconductor memory device has been tested. Although different manufacturers may vary this testing technique slightly, they cannot avoid conducting multiple write and read operations.
A primary problem associated with conventional testing techniques is that it is extremely time consuming and thereby costly to perform. For instance, a n.times.m memory device requires "n" write cycles to write "m" bits of data into the memory cells. As the semiconductor industry continues to create memory devices with greater memory capacity, testing costs will increase proportionately and become one of its highest manufacturing costs.
In order to alleviate rising testing costs, many semiconductor memory manufacturers have concentrated on improving read time access in an effort to lessen testing time. Additionally, at least Assignee corporation has begun to design and fabricate semiconductor memory devices having a standard internal design with a larger bit width than its number of I/O data pins. More specifically, a semiconductor memory device could be internally designed as a .times.8 device, but utilizes certain metal options to configure the device to operate as a .times.1 or .times.4 device. Although the memory device can be designed internally to be any size, it is generally designed internally to be a .times.8 device because it is the most common standard used by the computer industry.
Based on the foregoing, it would be desirable to have a capability of testing every memory cell in a memory device by reading and writing a large number of data bits in parallel in order to lessen testing time. Therefore, it is an object of the present invention to provide an apparatus and method for reading and writing in parallel a greater number of data bits during a single clock cycle than capable of being inputted into the memory device through its predetermined number of I/O data pins.
Another object of the present invention is to provide an apparatus and method for decreasing the monetary costs associated with conventional testing techniques.
A further object of the present invention is to provide an apparatus and method for decreasing the testing time associated with conventional testing techniques.